There is a growing demand for integrated circuits that can operate at different voltage supplies while also allowing different levels of input signals to be received by such circuits. For example, with computer graphics subsystems and other integrated circuits, core logic may be designed to operate at different voltage supply levels, such as 2.5 V or 1.8 V. Such chip cores or other circuits may be coupled to on chip input/output circuits such as input/output buffers which are connected to input/output pads or pins. These input/output pads or pins may then be connected to peripheral circuitry which may operate at several different input signal levels such as 1.5 V, 2.5 V or 3.3 V. With the increased demand for additional operational functions and integrated circuits, it is desirable to also increase operating frequency of such devices and decrease fabrication costs. As such, single gate oxide transistors have been proposed to be used on these integrated circuits. For example, a single 0.18 micrometer gate oxide length may be used for circuits that have a supply voltage of 1.8 V. The single gate oxide devices, may be, for example, CMOS transistors.
Because the core circuitry and I/O circuitry must interface with logic signals from other peripheral circuits that may have different input voltages or supply voltages, I/O circuit configurations may be structured to withstand 3.3 V or 2.5 V I/O voltage supplies despite normal 1.8 V based core logic circuits. Because the I/O buffers may require different multiple level supplies such as 3.3 V or 2.5 V voltage supply levels to interface with other circuits, a number of different input/output buffer circuits may be designed on a chip, so that depending upon the input signal level or I/O supply voltage level, one buffer configuration is activated over another. However, a problem arises during the powerup sequence if the core logic voltage, for example, is 1.8 V and if the I/O pad voltage supply is at a higher 3.3 V or 2.5 V level. Damage can occur to 30 .ANG. gate oxide thickness and 0.18 micrometer gate length devices due to potential overvoltage conditions if the I/O pad voltage supply appears first. This may occur because the correct I/O buffer circuitry has not been properly selected. For example, if the I/O pad voltage is powered up before the core supply voltage, the core supply voltage, if it were used to select a suitable I/O buffer circuitry, may not select a proper circuit and the higher I/O supply voltage may be inadvertently applied to 0.18 micrometer gate length I/O circuitry. Therefore, if the I/O pad voltage supply appears first, the 30 .ANG. gate oxide thicknesses and 0.18 micrometer, and 1.8 V CMOS transistors could be damaged.
Prior powerup sequence solutions have involved a printed circuit board level usage of voltage regulators that provide delay for I/O pad supply voltages as compared to the reference for the core voltage supply. With these circuits, the voltage regulator on a printed circuit board powers up the core voltage supply first and only alter that the I/O pad voltage supply is powered up. However, this solution typically means additional printed circuit board costs which can greatly reduce the competitive advantage of the increased functionality of the integrated circuits.
In addition, powerup sequencing circuits, if configurable on an integrated circuit, should not unnecessarily draw current during normal operating modes and should not decrease the electrostatic discharge protection capability of the integrated circuit or its chip.
Consequently, a need exists for a powerup sequencing circuit that may be configured on an integrated circuit that does not unnecessarily consume DC current during normal operating modes and does not decrease electrostatic discharge protection of a chip.